1. Field of the Invention
The present invention relates to a delay lock loop and delay lock method, and particularly relates to a delay lock loop, delay lock method, and delay lock updating method utilizing normal and/or reduced frequency in one or more delay loops.
2. Description of the Prior Art
FIG. 1 is a prior art delay lock loop 100. As shown in FIG. 1, the delay lock loop 100 includes a controllable delay line 103, a phase detector 105, and a delay control circuit 107. The controllable delay line 103 delays the input signal IS to generate an output signal OS according to a control signal CS from the delay control circuit 107. The phase detector 105 detects the phases of the input signal IS (a clock signal in this example) and the output signal OS to determine the phase relations there between (i.e which phase leads the other phase), thereby generates a phase detecting result. The phase detecting result is transmitted to the delay control circuit 107, which controls delay amount of the controllable delay line 103 according to the phase detecting result. By this way, a output signal OS having desired phase information can be acquired.
Besides above devices, the delay lock loop 100 can further comprise a plurality of buffers for signal synchronization, for example, buffers 101, 109, 111 and 113. In this example, the buffer 101 serves to buffer the input signal IS, the buffer 113 serves to buffer the output signal OS, the buffer 109 is a replica clock buffer, and the buffer 111 is a replica output signal buffer.
However, if the delay lock loop 100 operates at a high frequency, the power consumption is high, but has larger forward path delay if the delay lock loop 100 operates at a low frequency. This is a trade off for the delay lock loop 100.